1. Field of the Invention
The present invention relates to a high-level synthesis method for synthesizing a logic circuit from an operation string expressing an operation specification, and more particularly to a high-level synthesis method including a processing for optimizing the arithmetic sequence of an operation string.
2. Description of the Related Art
Procedure of synthesizing a logic circuit from operation specification conventionally employed (The High-level Synthesis of Digital System: MICHAEL C. McFARLAND, ALICE C. PARKER, PAUL CAMPOSANO: Proceeding of the IEEE, Vol. 78, No.2, 1990) is shown in FIG. 1.
According to the conventional procedure, an operation string is first extracted from the operation specification (Steps S101 and S103), scheduling is performed (Step S105) for the extracted operation string, hardware location (Step S107) is executed thereby roughly adapting a logic circuit, and finally a logic synthesis (Step S109) is performed in which circuit elements are allocated to the operation based on the results of the hardware allocation. Here, the Step S101 to Step S107 are the processing called "High-Level Synthesis."
By the scheduling in the Step S105, the corresponding relation between the operations and the duration of use of each arithmetic unit is determined so as to quicken the execution of the operation string under the restricted number of the arithmetic units which can be used simultaneously. For example, if the operation string extracted in the Step S103 is Z=H+((E+F)+(A-B+C+D+)+G)-I, then a logic circuit as shown in FIG. 2 was synthesized by the conventional procedure.
However, in the conventional High-level Synthesis, the linkage with the allocation of circuit elements are not considered sufficiently in the scheduling, and the optimization of the operation string is not performed even though the allocation of the circuit elements can be performed to the optimum in some cases by replacing the arithmetic sequence of the operation string. Because of this, there are shortcomings such as the scale of synthesized logic circuit is too large or the processing speed is not high.
Also, the scheduling is performed only based on the restricted number of the arithmetic units that can be used; and scheduling based on the information of initial circuit construction such as connecting relations between the arithmetic units is not performed. Because of this, the optimization of the operation string suited to the initial circuit construction has not been a performed and thus the conventional procedure has shortcomings of unutilizing the execution performance based on the initial circuit construction.